Differential amplifiers are being utilized in a wide field of application. For example, complementary signals are used in communication between electronic devices. Accordingly, a communication interface circuit, which is arranged in an electronic device, has a driver circuit that includes a differential amplifier to output complementary signals in response to complementary input signals. Japanese Laid-Open Patent Publication No. 2003-152523 describes an example of such a driver circuit.
As illustrated in FIG. 7, for example, the differential amplifier included in the driver circuit has inverters 71 and 72 and a differential current output driver 73. The inverters 71 and 72 receive complementary input signals IN and XIN, respectively. The differential current output driver 73 responds to output signals INa and XINa from the inverters 71 and 72. The differential current output driver 73 includes input transistors M71 and M72 which are activated and deactivated in a complementary manner in response to the input signals IN and XIN respectively. For example, when the input transistor M71 is activated to supply its drain current via an output terminal 74 to a signal wiring (cable), a terminating resistor R72 coupled to the input transistor M72, which is deactivated, terminates a signal wiring (cable) coupled to an output terminal 75. When the input transistor M72 is activated to supply its drain current via the output terminal 75 to the signal wiring (cable), a terminating resistor R71 coupled to the input transistor M71, which is deactivated, terminates the signal wiring (cable) coupled to the output terminal 74. In such a manner, the differential amplifier generates complementary output signals OUT and XOUT.
As illustrated in FIG. 8, in the differential amplifier illustrated in FIG. 7, there occurs a difference in transition timing between an output signal OUT and an inverted output signal XOUT. For example, the rising timing of the inverted output signal XOUT is delayed with respect to the falling timing of the output signal OUT. Further, since the output signals OUT and XOUT are complementary to each other, the rising timing of the output signal OUT is also delayed with respect to the failing timing of the inverted output signal XOUT.
As illustrated in FIG. 9, when the internal signal INa rises at time T1, the on-resistance of the input transistor M71 that receives the internal signal INa increases. This decreases a current flowing through the input transistor M71 and lowers the output signal OUT. Further, the internal signal XINa falls at time T1. When the voltage of the internal signal XINa supplied to the gate of the input transistor M72 is lowered below a voltage obtained by subtracting a total sum of the source-drain voltage of a constant current transistor M73 and the threshold voltage Vth of the input transistor M72 from a high potential voltage VDD, the input transistor M72 is activated (time T2). Then, a current flows to the resistor R72 via the activated input transistor M72 to raise the inverted output signal XOUT. In such a manner, the input transistors M71 and M72 are activated and deactivated at different timings.
Thus, with respect to the timing at which one of the output signals OUT and XOUT changes in potential from the high level to the low level, the timing at which the other of the output signals OUT and XOUT changes in potential from the low level to the high level is delayed. Therefore, due to the delay (that is, skew) in timing between the complementary output signals OUT and XOUT, the cross-point of the output signals OUT and XOUT shifts from the midpoint amplitude of each of these signals OUT and XOUT. Such a shift in cross-point of the output signals OUT and XOUT from the midpoint amplitude deteriorates the quality of data to be transmitted.